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Preliminary
Features
* *
RF Single Chip for Cordless Phone
* *
HT9015
* *
Operating voltage: 2.7V~6V Extremely low power consumption current -I CC= 0mA (typ.) in battery-saving mode -I CC= 8.5mA (typ.) in standby mode -I CC= 13.5mA (typ.) for communication Built-in IF decoder, compander and PLL IF decoder - 1st/2nd Mixers, RX VCO - RSSI quadrature detector, IF AMP - Noise detector
*
Compander - Expander, Compressor, Limiter - Receive AMP, MIC AMP, PRE AMP PLL - RX PLL, TX PLL - Local oscillator - Data latch control - Unlock detector Four threshold variable battery alarms
General Description
The HT9015 is an RF single chip for cordless phone systems. Internally these are three major parts, a PLL, an IF decoder and a compander. The PLL provides radio channel selection for either the transmitter or receiver. Frequency locking status of the selected channel can be monitored by a control register. The IF decoder provides two frequency down converters that let high frequency signals pass through a mixer and local oscillator to be lowered for frequency even base band signals. It also provides an RSSI (receiver signal strength indicator) function to detect the IF output signal strength and built-in noise detector for S/N quality. The compander provides better S/N ratio for audio signal processing. The HT9015 has a wide-range applications in FM/FSK, Transmitting/Receiving of VHF bandwidth including cordless phone, narrow band voice and data transceiver systems. The most significant advantage of the HT9015 is in the reduction of many external components making it well suited for cordless phone baseset, handset radio section.
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April 10, 2000
Preliminary
Block Diagram
GND2 5 TX_O UT 4 3 2 R X_O U T C_RECT VCO2 VCO1 1 48 VC O _CO NT 47 VCC2 46 1 S T M IX _ IN 45 44 T X _ IN 6 TX PLL RX PLL RX VCO R e g u la to r 1st M ix e r 43
HT9015
VREF 1 S T M IX _ O U T
VCC3 7
42 8 9 LO OSC 2nd M ix e r 41
E_RECT
LO 1 LO 2
2 N D M IX _ IN
40 S IG _ O U T CLK DATA STB 10 39 11 12 13 D a ta L a tc h C o n tro l Low BAT A la r m 38 37 14
N_REC
2 N D M IX _ O U T
VCC1
IF _ IN
F IL _ O U T
IF AMP
36 35 34
DEC GND1
LPF F IL _ IN 15 C_M UTE 16
C o m p re s s o r
L im ite r
RSSI
IF _ O U T
Q uad D e te c to r
33
QUAD
CO M P_O UT
E xpander
C_NF
17 18
E_M UTE
LPF
32
AF_O UT
M IC _ O U T
M IC AMP
PRE AMP
Com p a ra to r
R e c e iv e r AMP
31 N o is e F ilte r
N _ F IL _ O U T
30 M IC _ IN 19
D a ta Com p
N _ F IL _ IN
20
P R E _ IN
21
22
23
24
RO1
25
RO2
26
BAT_ALM
27
28
29
D _ C O M P _ IN
P R E _ O U T E X P _ O U T R E C E _ IN
RSSID_CO M P_O UT
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April 10, 2000
Preliminary
Pin Assignment
VCO2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C_RECT RX_O UT TX_O U T GND2 T X _ IN VCC3 LO 1 LO 2 S IG _ O U T CLK DATA STB F IL _ O U T F IL _ IN CO M P_O UT C_NF M IC _ O U T M IC _ IN P R E _ IN PR E_O U T EXP_O U T R E C E _ IN RO1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCO1 VCO _CO N T VCC2 1 S T M IX IN VREF 1 S T M IX O U T E_R EC T 2 N D M IX IN N_REC 2 N D M IX O U T VCC1 IF _ IN DEC GND1 IF _ O U T QUAD AF_O UT N _ F IL _ O U T N _ F IL _ IN D _ C O M P _ IN D_CO M P_O UT RSSI BAT_ALM RO2
HT9015
H T9015 48 SSO P
Pin Description
Pin No. 1 2 3 Pin Name VCO2 C_RECT RX_OUT I/O I 3/4 O Description Connects LC network with VCO1 pin to provide the tank circuit for the received voltage control oscillator Normally connected to ground through a capacitor. Receiver phase detector output. The PDT of RX-PLL detects phase errors from the received PLL. The output is connected to external low pass filter. Transmitter phase detector output. The PDT of TX-PLL detects phase errors from the transmitted PLL. The output is connected to an external low pass filter. Digital ground 14-bit programmable transmit counter input. The output signal from the external VCO circuit can be AC coupled to this pin.
4 5 6
TX_OUT GND2 TX_IN
O 3/4 I
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April 10, 2000
Preliminary
Pin No. 7 8 9 Pin Name VCC3 LO1 LO2 I/O 3/4 I O Description Positive power supply for digital block circuits.
HT9015
This pin connects to LO2 pin with external crystal and capacitor. This output pin generates a reference frequency used for the PLL and the second mixer local oscillator when connected to LO1 pin with an external crystal and capacitor. This pin outputs four-type states and is selected by an internal control register. There are RSSI state and noise state and RX/TX PLL lock states. Open drain output. Clock input pin Serial data input pin Data strobe control pin Splatter filter output pin Splatter filter input pin Compressor output pin Normally connected to ground through a capacitor. Microphone amplifier output pin Microphone amplifier input pin Pre-amplifier input pin Pre-amplifier output pin Expander output pin Receiver amplifier input pin Receiver amplifier output pin Receiver amplifier output pin Battery alarm output pin. When the battery voltage is lower than the internal setting threshold this pin is active. Open drain output. Receiver signal strength indicator output pin, the output signal depends on the IF amplifier output signal. Data comparator output pin Data comparator input pin. Input to comparator to distinguish digital data from audio. Input to noise filter Output from noise filter
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SIG_OUT CLK DATA STB FIL_OUT FIL_IN COMP_OUT C_NF MIC_OUT MIC_IN PRE_IN PRE_OUT EXP_OUT RECE_IN RO1 RO2 BAT_ALM RSSI D_COMP_OUT D_COMP_IN N_FIL_IN N_FIL_OUT
O I I I O I O 3/4 O I I O O I O O O O O I I O
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April 10, 2000
Preliminary
Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name AF_OUT QUAD IF_OUT GND1 DEC IF_IN VCC1 2NDMIX_OUT N_REC 2NDMIX_IN E_RECT 1STMIX_OUT VREF 1STMIX_IN VCC2 VCO_CONT VCO1 I/O O I O 3/4 3/4 I 3/4 O 3/4 I 3/4 O O I 3/4 I I Description
HT9015
FM demodulator output pin. Output signal frequency is within the audio band. Normally provides a 455kHz carry frequency for the FM quadrature detector. IF amplifier output pin. Signal will later pass through external 90C phase shifter for quadrature detector. Analog ground Normally connected to VCC1 through a capacitor. IF amplifier input pin it is necessary to use the IF filter network to get high quality IF signal. Analog power supply Second mixer IF signal output pin and down converter. IF frequency is 455kHz. Connect to ground through capacitor. Second mixer RF signal input pin and down converter. Frequency is 455kHz. Expander rectifier filter capacitor pin. First mixer IF signal output pin and down converter. IF frequency is 10.7MHz. Reference voltage input for compander. The first mixer RF signal input. Carrier frequency from 20~60MHz. Directly connects to the two voltage regulators inside. Normally connected to ground through a capacitor. Connects LC network with VCO2 pin to provide the tank circuit for the received voltage control oscillator.
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to 6V Input Voltage .................VSS-0.3V to VCC+0.3V Storage Temperature.................-55C to 150C Operating Temperature ..............-20C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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April 10, 2000
Preliminary
Electrical Characteristics
Symbol VCC ICC1 ICC2 ICC3 ICC4 ICC5 ICC(A) ICC(BS) IREF VIH VIL IIH IIL fCK Regulator Symbol VREG IOUT (MIN) Detector Symbol VBAT-L VBAT-H VBAT-L VBAT-H Parameter Detection Voltage 1 Detection Voltage 1 Detection Voltage 2 Detection Voltage 2 Test Conditions VCC 3.6V 3.6V 3.6V 3.6V
6
HT9015
Ta=25C
Parameter Operating Voltage Current 1 Consumption Current 2 Consumption Current 3 Consumption Current 4 Consumption Current 5 Consumption Current Alarm Supply Supply Current in Battery Saving Mode VREF Voltage Data Input Threshold Data Input Threshold Data Input Current Data Input Current CK Input Frequency
Test Conditions VCC 3/4 Conditions VCC1=VCC3
Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Typ. 3.6 13.5 8.5 3.5 2.1 1.7 100 0 1.5 VCC3 0 0 0 38
Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1000
Unit V mA mA mA mA mA mA mA V V V mA mA kHz Ta=25C
3.6V All on 3.6V RX-RF ON 3.6V RX-AF ON 3.6V TX-RF ON 3.6V TX-AF ON 3.6V RL= 100kW 3.6V All off 3.6V 3.6V 3.6V 3/4 3/4 3/4
3/4 3/4 3/4 3/4 3/4 3/4
3.6V VIH= VCC 3.6V VIL= GND 3.6V 3/4
Parameter Output Voltage Minimum Load Current
Test Conditions VCC Conditions VOUT= VREG (Open)-0.05V 3.6V IOUT= 1mA 3.6V
Min. 1.7 3/4
Typ. 2 3
Max. Unit 2.3 3/4 V mA Ta=25C
Conditions 3/4 3/4 3/4 3/4
Min. 3/4 3/4 3/4 3/4
Typ. 3.3 3.37 3.15 3.2
Max. 3/4 3/4 3/4 3/4
Unit V V V V
April 10, 2000
Preliminary
Symbol VBAT-L VBAT-H VBAT-L VBAT-H VOL ILEAK VTH VOL ILEAK VTH-H VTH-L VOL ILEAK VTH-L VTH-H VHYS Parameter Detection Voltage 3 Detection Voltage 3 Detection Voltage 4 Detection Voltage 4 Output Low Level Voltage Output Leak Current Minimum Detection Level Output Low Level Voltage Output Leak Current Noise Detection Level Noise Detection Level Noise Detection Level Voltage Output Leak Current RSSI Comparator Detection Voltage RSSI Comparator Detection Voltage RSSI Comparator Hysteresis Test Conditions VCC 3.6V 3.6V 3.6V 3.6V Conditions 3/4 3/4 3/4 3/4 Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3.05 3.10 2.78 2.82 0.1 0 3/4 0.1 0 0.57 0.47 0.1 0 0.72 0.8 0.08
HT9015
Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Unit V V V V V mA mVrms V mA V V V
mA
3.6V ISINK= 0.1mA 3.6V VALM= 3.6V 3.6V f= 500Hz 3.6V ISINK= 0.2mA 3.6V VDATA= 3.6V 3.6V 3.6V 3/4 3/4
3.6V ISINK= 0.2mA 3.6V VSIG= 3.6V 3.6V 3.6V 3.6V Comparator Output L (R) H Comparator Output H (R) L 3/4
V V V
PLL Detection Symbol fIN VIN VLO ICP1 ICP2 ILEAK fLO Parameter Operating Frequency TX-PLL Input Sensitivity Local Oscillator Input Sensitivity Charge Pump Output Current Charge Pump Output Current Charge Pump Leak Current Local Oscillator Operating Frequency
dBmV=dBmV EMF (Open), Ta=25C Test Conditions VCC 3.6V 3.6V Conditions 3/4 3/4 Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. Max. Unit 46.61 103 110 200 400 0 10.24 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MHz dBmV dBmV mA mA mA MHz
3.6V fLO= 10.240MHz 3.6V VCP= 1.8V 3.6V VCP= 1.8V 3.6V 3/4
3.6V VLO= 112dBmV
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April 10, 2000
Preliminary
RX-VCO IF + MIX section
HT9015
fIN (MIX 1)=46.61MHz, fIN (IF)=455kHz, Df=3kHz fm= 1kHz, dBmV=dBmV EMF (Open), Ta=25C Symbol KV VVCO Parameter Conversion Gain Test Conditions VCC 3.6V Conditions 3/4 Min. 3/4 3/4 Typ. 1 110 Max. 3/4 3/4 Unit MHz/V dBmV Ta=25C Test Conditions VCC Conditions Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. Max. 20 46.61 10.7 26 75 220 55 40 2.1 3.5 5.8 2.5 1.5 330 1.5 1 2.4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Unit dBmV MHz MHz dB dB mVrms dB dB kW pF kW pF kW W kW V V
RX VCO Oscillation Level 3.6V fVCO= 25~55MHz
1st and 2nd Mixer, IF AMP Symbol 12dB SINAD fMIX1 fMIX2 GVC GIF VOD S/N AMR RIN1 CIN1 RIN2 CIN12 RIN RO1 RO2 VRSSI1 VRSSI2 Parameter
12dB SINAD Sensitivity 3.6V Input 50W Mixer Operating Frequency Mixer Operating Frequency Conversion Gain IF AMP Gain Demodulated Output S/N Ratio AM Rejection Ratio Input Impedance Input Impedance Input Impedance Input Impedance Input Resistance Output Resistance Output Resistance RSSI Output Voltage RSSI Output Voltage 3.6V 1STMIXER 3.6V 2NDMIXER 3.6V Excluding Filter Loss 3.6V 3/4 3.6V VIN (MIX 1)= 70dBmV 3.6V VIN (MIX 1)= 70dBmV 3.6V VIN (MIX 1)= 70dBmV 3.6V 1st MIX IN 3.6V 1st MIX IN 3.6V 2nd MIX IN 3.6V 2nd MIX IN 3.6V IF IN 3.6V 1st MIX OUT 3.6V 2nd MIX OUT 3.6V VIN (MIX 1)= 20dBmV 3.6V VIN (MIX 1)= 60dBmV
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April 10, 2000
Preliminary
Compressor + MIC AMP Symbol Vrefc VOC V4 tHDC VNOC Vlim1 Vlim2 VMUTE Parameter Input Reference Level Output Deviation MIC AMP Voltage Gain Output Noise Level Limiting Level Limiting Level Mute Output Level Test Conditions VCC Conditions 3.6V VOM=-10dBV 3.6V VOM=-30dBV 3.6V 3.6V Input-GND Short 3.6V COMP Out, VIM= 0dBV 3.6V MIC Out, VIM= 0dBV 3.6V 3/4 3/4 3/4 3/4 3/4 3/4 Min.
HT9015
fIN=1kHz, Ta=25C Typ. Max. Unit -10.5 -0.2 20 0.3 -61 1.3 2.6 -96 3/4 3/4 3/4 3/4 dBV dB dB % dBV VP-P VP-P dBV Ta=25C
Total Harmonic Distortion 3.6V VOM=-10dBV
Expander + PRE AMP + Receiver AMP Symbol VrefE VOE GP3 THD1 VMUTE GRNG2 GRNG1 CTCE GS DRS Parameter Input Reference Level Output Deviation PRE AMP Voltage Gain Test Conditions VCC Conditions 3.6V VOP=-10dBV 3.6V VOP=-35dBV 3.6V 3/4 RL= 150W VRI=-15dBV 3/4 3/4 3/4 Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Typ. Max. Unit -10 0.5 0 0.5 -76 0 6 -95 0 3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 dBV dB dB % dBV dB dB dB dB VP-P
Total Harmonic Distortion 3.6V Mute Output Level PRE AMP Voltage Gain Setting Range Receiver AMP Voltage Gain Setting Range Crosstalk CE Voltage Gain Maximum Output Level 3.6V 3.6V 3.6V
3.6V VIM=-20dBV 3.6V 3.6V THD= 3%
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April 10, 2000
Preliminary
Functional Description
The HT9015 is a signal chip RF IC for cordless phone applications. It has applications for 46/49MHz cordless phones as well as CT0 cordless phones that have frequency bands between 20MHz and 60MHz. This chip enables external components in the base set and hand set radio section application circuits to be reduced. The HT9015 is manufactured or a special process called BiCMOS, or bipolar process and CMOS process. Because the RF and IF parts need high frequency actions such as mixer, VCO, IF amplifier and demodulator, those parts are implemented in high performance bipolar circuits. The other digital functions are designed using CMOS circuits. Sometimes this chip is known as COMBO, the meaning of COMBO is one chip combined with RF, IF and PLL parts. The HT9015 provides data latch interface controlled by a microcontroller. There are four internal registers inside the HT9015; TX (transmitter) divider, RX (receiver) Divider, REF (reference) divider and Control Register. All registers can be set through the data latch control interface. The data latch control interface contains DATA, CLK and STB control signals. Input timing for serial data Data is read on the timing of the rising edge of CLK. When STB receives a high signal, DATA
1ms
0 .2 m s
HT9015
in the shift register is sent into the latch to control the block, see the input timing for serial data as shown below. Serial data format of four registers According to previous input timing Specs, the HT9015 can be easily set up using four registers. The TX divider determines the TX PLL locked frequency; the RX divider determines the RX PLL locked frequency; the REF divider determines the TX and RX PLL frequency reference which is also called channel space. The control register is an important unit which controls the radio link, voice control and power saving during base set and hand set communication. All data format contains 20 bits, but some registers need only 16 bits, They have a common field of 20 bits data format called code which determine what data belongs to whom. See the table below. Code 1 1 0 0 1 0 1 0 Register REF register TX register RX register Control register
Four register selection
0 .2 m s
C LK DATA
0 .2 m s
0 .1 m s
0 .1 m s
0 .2 m s
STB
0 .2 m s
O p e r a tio n
S ta te
P r e v io u s S ta te
N ew
S ta te
Figure 1 Input timing for serial data
10 April 10, 2000
Preliminary
* REF register
HT9015
Divide number range is from 5 to 4095. This register includes TEST bits which must be set to 0.
D o n 't C a r e T e s t 0 1st BC R0 R1 R2 R3 1 2 - b it R R4 R5 C o u n te r R6 R7 R8 R9 R 10 R 11 Code 1 1 STB
Divide number:
R= R0 + R1 2 + R2 2 + R3 2 + 1/4 + R11 2 BC bit is BATTERY ALARM detection setting.
* TX register
2
3
11
Divide number range is from 5 to 16383.
S D o n 't C a r e N0 1st N1 N2 N3 N4 1 4 - b it N N5 N6 C o u n te r N7 N8 N9 N10 N11 N12 N13
Code 1 0 STB
Divide number:
N= N0 + N1 2 + N2 2 + N3 2 + 1/4 + N12 2
* RX register
2
3
12
+ N13 2
13
Divide number range is from 5 to 16383.
D o n 't C a r e N0 1st N1 N2 N3 N4 1 4 - b it N N5 N6 C o u n te r N7 N8 N9 N10 N11 N12 N13 Code 0 1 STB
Divide number:
N= N0 + N1 2 + N2 2 + N3 2 + 1/4 + N12 2
* Control register
2
3
12
+ N13 2
13
This register includes battery saving control for the TX/RX circuits or MUTE controls for the commander block or changing threshold level for the battery alarm.
D o n 't C a r e TXLD 1st S IG R XLD OUT RSSI ND RF AF TX CP M UTE RF AF RX CP M UTE BA1 BAT BA2 0 Code 0 STB
L D , R S S I, N D S e le c tio n
B a tte ry S a v in g
C h a rg e C O M P Pum p M UTE C u rre n t
B a tte ry S a v in g
C h a rg e E X P Pum p M UTE C u rre n t
BATTERY ALARM T h r e s h o ld
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April 10, 2000
Preliminary
Battery saving control
HT9015
0 1/41/41/41/4Operation Bit TX-RF TX-AF RX-RF RX-AF
MUTE control
1 1/41/41/41/4Battery saving Control Block TX-RF= 1 and RX-RF= 1 LOCAL OSC= OFF
TX-PLL MIC AMP, Compressor, Splatter
RX-VCO, RX-PLL, 1st MIX, 2nd MIX IF AMP, NOISE DET, DATA COMP, RSSI Pre AMP, Expander, Receiver AMP
0 1/41/41/41/4normal
1 1/41/41/41/4MUTE
MUTE for Compressor output. These bits prevent the compander block going into a battery saving mode. Current consumption therefore does not decrease.
Charge pump current control
PLL loop performance such as lock-up time can be changed by these control bits. Bit TX CP RX CP Control Output TX-PLL Charge Pump Output Current RX-PLL Charge Pump Output Current 0 200mA 200mA 1 400mA 400mA
BATTERY ALARM detection setting
There are has four threshold levels for low battery detection. These threshold levels are shown on the table below.
(1)
BC
BA1 0 0 1 1 0 1
BA2 0 1 0 1 0 1
(2)
VBAT-L 3.00V 3.25V 3.30V 3.45V Battery Saving
0 0 0 0 1 1
(1) (2)
BC bit in REF divider Only for BATTERY ALARM block
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April 10, 2000
Preliminary
SIG_OUT selection
HT9015
The SIG_OUT terminal generates combination states of RX and TX lock detectors. The RSSI and NOISE detector are shown in figure 2 below. SW1 and SW2 in Fig. 3 determine the output on SIG_OUT using selection bits in a control register according to the figure below.
LDTX
LDRX
RSSI
ND
D e c id e S W 1 and LD O UT
D e c id e S W 2 and D ET O UT
E x a m p le : T X lo c k d e te c to r o p e r a tio n LDTX 1 LDRX 0 RSSI 0 ND 0
Figure 2 SIG_OUT bits
R X PLL
LO C K D ETEC TO R RX LD
SW 1 LD OUT S IG _ O U T
TX LD
TX PLL IF A M P
SW 2
DET OUT
N O IS E D E T E C T O R RSSI
RSSI
In te rn a l E x te rn a l
RSSIDET
ND
N_REC
N _ F IL _ O U T
N _ F IL _ IN
AF OUT
Figure 3 Signal output block diagram
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April 10, 2000
Preliminary
* Example of divider setting
HT9015
When the LOCAL OSC frequency is 10.240MHz, RX VCO has to oscillate at frequencies from 35.915MHz in 20kHz or 25kHz step.
Reference frequency at the PHASE DETECTOR should be set to 5kHz. 10.240MHz 5kHz = 2048, \ R= 2048 Calculate dividing number N for RX divider 35.915MHz 5kHz = 7183, \ N (CH16)= 7183 35.935MHz 5kHz = 7187, \ N (CH17)= 7187 Finally you set the following registers.
R X D iv id e r fo r 7 1 8 3 N 1 1st R E F D iv id e r fo r R = 2 0 4 8 TestB C 1 1 1st 0 0 0 0 0 0 0 0 0 0 0 1 Code 1 1 STB 1 1 1 0 0 0 0 0 0 1 1 1 0
Code 0 1 STB
* The power saving arrangement is one of the features in the HT9015.
This is achieved through an inside control register to arrange the power consumption of the three major parts (RF. IF. PLL). There are two-pair DC power supplies for the HT9015, VCC1-GND1 and VCC3-GND2. The DC power VCC1 provides operating voltage for the IF detector and the compander analog parts. The DC power VCC3 provides the operating voltage for the PLL and data latch control. It also has a built in 2.0V regulator VCC2 for the RX front end. See the power supply arrangement as shown on the table below. VCC1 VCC3 GND1 GND2 1st MIX, 2nd MIX, IF AMP, QUAD, NOISE DET. RX-VCO DATA COMP, COMPANDER, RECEIVER AMP, SPLATTER. RX-PLL, TX-PLL, LOCAL OSC, DATA LATCH CONTROL
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April 10, 2000
Preliminary
Intermediate frequency (IF) decoder part The figure below shows a simplified block diagram for a double-conversion super heterodyne FM receiver. Heterodyne means to mix two frequencies together in a non linear device or to translate one frequency to another using non linear mixing. The super heterodyne receiver is an improvement over other receiver in gain, selectivity, and sensitivity characteristics. The super heterodyne receiver is divided into five parts:
* RF section. Generally consists of a preselector * Mixers
HT9015
and an amplifier stage.
* Mixer conversion section. Includes a ra-
dio-frequency oscillator stage (commonly known as a local oscillator) and a mixer conversion stage (commonly known as a frequency detector) to produce the IF signal. * The IF section. Generally consists of a series of IF amplifiers and bandpass filters and known as the IF strip. Most of the receiver gain and selectivity is achieved in the IF section. * The FM demodulator section: The quadrature FM demodulator uses a 90 phase shift, a single tuned circuit, and a product detector to demodulate the FM signals. * The audio amplifier section. The audio section comprises several cascaded audio amplifiers and one or more speakers. The number of amplifiers used depends on the audio signal power desired.
R e c e iv e a n te n n a 1 s t_ M ix o u t 2 n d _ M ix in P r e s e le c to r R F - a m p lifie r In te rn a l RF 1 s t M ix e r 1 s t IF 2 n d M ix e r 2nd Lo_osc ( C r y s ta l) 2 n d _ M ix o u t
A Mixer is a non linear device whose purpose is to convert radio frequencies (RF) to intermediate frequency (IF) (RF-to-IF frequency translation). In the frequency conversion process, RF signals are combined with the local oscillator frequency in a non linear device. The output of the mixer contains an infinite number of harmonic and cross-product frequencies which include the sum and the difference between the desired RF carrier and the local oscillator frequencies. The IF band-pass filter are tuned to the different frequencies. Therefore, the IF signal is filtered out by the BPF. In the HT9015 the double conversion method (Figure 4) is applied to produce the lower IF.
(1 0 .7 M H z ) RF 1stLo_osc (R X _ V C O ) C e r a m ic F ilte r 1 s t IF (4 5 5 k H z ) C e r a m ic F ilte r 2 n d IF
2nd Lo_osc ( C r y s ta l)
Figure 4 The illustration of mixers The first IF is a relatively high frequency (10.7MHz), for good image-frequency rejection, while the second IF is a relatively low frequency (455kHz) that allows the IF amplifiers to have a relatively high gain and still not be susceptible to oscillations.
N _ F IL _ O U T
N _ F IL _ IN
AF_O UT
IF _ O U T
QUAD
IF _ IN 2 n d IF IF _ A M P
DEC
Q u a d ra tu re D e te c to r
LPF
N o is e F ilte r
1stLo_osc (R X _ V C O )
RSSI
N o is e C O M P
D _ C O M P _ IN D a ta C O M P
RSSICO M P
D_CO M P_O UT RSSI
Figure 5 Intermediate frequency decoder block
15 April 10, 2000
Preliminary
* Limiting IF Amplifier, RSSI (Received Signal
HT9015
Strength Indicator) and RSSI Comparator
* Quadrature detector
The basic function of the IF amp is to boost the IF signal and to help handle impulse noise. The IF limiter applies very high gain to the IF frequency such that the top and bottom of the waveform are clipped. This helps in reducing AM and noise intercepted upon reception. The limiting IF amplifier consists of four differential amplifiers (Figure 6).
Once the signal leaves the IF section, it must be demodulated so that the baseband signal can be separated from the IF signal. This is accomplished by the quadrature detector. A quadrature detector (Figure 7) uses a 90 phase shifter (Ci), an L/C tuned circuit, and a phase comparator to demodulate FM signals.
L C -T a n k IF -O U T
DEC O F -IN 2 n d IF
AMP1
AMP2
AMP3
AMP4 In te rn a l S (R S S I)
Q u a d ra tu re D e te c to r
Figure 6 Limiting IF Amplifier, RSSI and RSSI comparator
V
DD
L
C
R
L C -T a n k IL 1
D iffe r e n tia l to S in g le - E n d e d C o n v e r te r IL 2 LPF
D e m o d u la tio n S ig n a l f0 = 4 7 k H z
C
i
V
O
B u ffe r I1 I2
IF _ A M P V
i
I= I1 + I2
Figure 7 Quadrature detector
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April 10, 2000
Preliminary
* Noise detector
HT9015
Figure 8 is a band pass filter which can detect noise energy on N_REC pin. There is also a pass through the noise comparator to determine two states on SIG_OUT pin by internal
V B a n d - P a s s F ilte r FO=31kH z N o is e F ilte r N _ F IL _ IN V
OUT
control register setting. The high state expresses noise level more than 0.4V and the low state expresses noise level under 0.4V.
DD
H ig h - P a s s F ilte r FC=25kH z N o is e C o m p a r a to r N o is e D e t. N_REC C4 In te rn a l E x te rn a l
E x te rn a l R4
R5 AMP C3
N _ F IL _ O U T R3
A u d io S ig n a l R1 R2
C1
C2
Figure 8 Noise detector
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April 10, 2000
Preliminary
Compander The compander (compressor and expander) is composed of two variable gain circuits which provide compression and expansion of the signal dynamic range. In consideration of the wide band noise and maximum dynamic range which exist in the transmission medium, the general signal handling technique lowers the general communication quality by reducing the S/N ratio and generating a clipping phenomenon. However the compander improves the communication quality by automatically controlling the gain based on the input signal level to increase the valid dynamic range and to improve the S/N ratio.
C o m p re s s o r O u tp u t
HT9015
In the HT9015, the compressor will take a signal with a 75dB dynamic range (-5dB to -80dB), and reduce it to a 37.5dB dynamic range (-7.5dB to -45dB) by attenuating strong signals,while amplifying low level signals. The expander does the opposite in that the 37.5dB signal range is increased to a dynamic range of 75dB by amplifying strong signals and attenuating low level signals. The 0dB level is internally set at 316.227mVrms - that is the signal level which is neither amplified nor attenuated. See Figure 9 below. Through the action of the compander, the noise of the transmission medium is constant under -80dBV.
E xpander O u tp u t
C o m p re s s o r In p u t
E xpander In p u t T r a n s m is s io n M e d iu m
0dBV -5dBV - 1 0 .5 d B V -20dBV -30dBV -40dBV -50dBV -60dBV -70dBV -80dBV N o is e - 4 5 .2 5 d B V - 2 5 .2 5 d B V - 7 .7 5 d B V
0dBV -5dBV - 1 0 .5 d B V -20dBV -30dBV -40dBV -50dBV -60dBV -70dBV -80dBV
- 1 5 .2 5 d B V
- 3 5 .2 5 d B V
Figure 9 Illustration of compressed and extended signal
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April 10, 2000
Preliminary
PLL The figure below shows a simplified block diagram of the programmable universal dual phase-locked loop (PLL). It provides accurate channel frequencies for cordless phone. The PLL contains one 14-bit programmable counter, one phase detector, charge pump, unlock detector and the 2nd local oscillator. The 12-bit programmable counter provides the ref-
HT9015
erence frequency for the receiver (RX) and transmitter (TX) loops. This dual PLL is fully programmable through the mC serial interface and supports most country channel frequencies including USA, Spain, Australia, Korea, New Zealand, U.K., Netherlands, France, Taiwan, and China.
VC O _CO NT VCO1 VCO2 R X_O U T
R X_VC O 1 4 - B it R X C o u n te r 1 2 - B it R E F C o u n te r LO CAL O s c illa to r D a ta L a tc h R e g is te r LO 2 LO 1
C h a rg e P U M P (R X )
P hase D e te c to r (R X )
TX_O UT
C h a rg e P U M P (T X )
P hase D e te c to r (T X )
1 4 - B it T X C o u n te r
Figure 9 PLL block diagram
T X _ IN
CLK
DATA
STB
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April 10, 2000
CF1 1 0 .7 M H z 455kH z VCC1 VCC1 CD ~ ~ C13 2 .2 m F 1 S T M IX _ O U T 1 S T M IX _ IN 2 N D M IX _ O U T 2 N d M IX _ IN E_RECT N_REC VCC1 IF _ IN DEC GND1 IF _ O U T QUAD AF_O UT R F IN 4 6 .6 1 M H z L10 46 VCC2 C11 10mF C12 1000pF C9 45 44 VREF 43 42 41 40 39 38 37 36 35 34 33 C17 2 .2 m F C29 91pF C19 1000pF C24 0 .1 m F C21 C23 2 2 m F 0 .1 m F C25 0 .1 m F ~ R15 1 .5 k W C32 R17 R18 3 .3 k W ~ ~ ~ C30 10mF R16 R22
R9 330W
A u d io O u tp u t
C38 1mF
C23 C34 R19 220pF 220pF 50kW 30 N _ F IL _ IN 32 31 N _ F IL _ O U T 29 D _ C O M P _ IN 28 D_CO M P_O UT 27 RSSI BAT_ALM 26 RO2 25 RO 1 24 R E C E _ IN EXP_O UT PR E_O UT 23 22 21 P R E _ IN 20 R24 20kW M IC _ O U T C37 1mF 1000pF R27 100kW
R27 100kW
VCC1
VCC1
Preliminary
VCC2 C101 10000pF C102 0 .2 2 m F 1 2 C_RECCT 3 R X -O U T 4 TX_O UT 5 VCC3 GND2 T X _ IN 6 C9 1000pF C8 0 .1 m F VCO VCC3 X 't a l 1 0 .2 4 0 M H z C18 10mF 7 8 LO 1 LO 2 VCO2 R101 15kW C103 10000pF C111 10000pF C112 0 .2 2 m F R112 10kW C113 10000pF R111 15kW C14 10mF R102 5 .1 k W L11 C15 48 VCO1 V C O -C O N T 47
C10 0 .1 m F
H T9015 48 SSO P
R R26 20kW R25 20kW
R E C E IV E R
C39 1mF CO M P_O UT S IG _ O U T F IL _ O U T F IL _ IN R23 20kW DATA C_NF CLK STB M IC _ IN
C20
9 R10 100kW
10
11
12
13
14 C27 R12 10kW 10kW 10kW VCC3 C22 R11 C26
15 R13
16 R14 C31 10mF C28
17
18 R20 20kW
19
Application Circuits
R21 2kW C36 1mF T S IG DATO OUT CLK DATA STB M IC
M ic r o c o n tr o lle r
DATI
K e y b o a r d & L C D In te r fa c e
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April 10, 2000
HT9015
VCC1
Preliminary
China CT0 frequency
* Base set
HT9015
Channel Number 1 2 3 4 5 6 7 8 9 10
* Hand set
TX Channel Frequency (MHz) 45.250 45.275 45.300 45.325 45.350 45.375 45.400 45.425 45.450 45.475
RX Counter Value TX Counter Value fIN-R Input (Ref. Freq.= (Ref. Freq.= Frequency (MHz) 5.00kHz) 5.00kHz (1st IF= 10.7MHz) 9050 9055 9060 9065 9070 9075 9080 9085 9090 9095 37.550 37.575 37.600 37.625 37.650 37.675 37.700 37.725 37.750 37.775 7510 7515 7520 7525 7530 7535 7540 7545 7550 7555
Channel Number 1 2 3 4 5 6 7 8 9 10
TX Channel Frequency (MHz) 48.250 48.275 48.300 48.325 48.350 48.375 48.400 48.425 48.450 48.475
RX Counter Value TX Counter Value fIN-R Input (Ref. Freq.= (Ref. Freq.= Frequency (MHz) 5.00kHz) 5.00kHz (1st IF= 10.7MHz) 9650 9655 9660 9665 9670 9675 9680 9685 9690 9695 34.550 34.575 34.600 34.625 34.650 34.675 34.700 34.725 34.750 34.775 6910 6915 6920 6925 6930 6935 6940 6945 6950 6955
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April 10, 2000
Preliminary
U.S.A. CT0 frequency (10 channels)
* Base set
HT9015
Channel Number 1 2 3 4 5 6 7 8 9 10
* Hand set
TX Channel Frequency (MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970
RX Counter TX Counter Value fIN-R Input (Ref. Freq.= Frequency (MHz) Value (Ref. Freq. = 5.00kHz) 5.00kHz (1st IF= 10.695MHz) 9322 9326 9334 9342 9346 9354 9366 9374 9386 9394 38.975 39.150 39.165 39.075 39.180 39.135 39.195 39.235 39.295 39.275 7795 7830 7833 7815 7836 7827 7839 7847 7859 7855
Channel Number 1 2 3 4 5 6 7 8 9 10
TX Channel Frequency (MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970
TX Counter Value (Ref. Freq.= 5.00kHz 9934 9969 9972 9954 9975 9966 9978 9986 9998 9994
fIN-R Input Frequency (MHz) (1st IF= 10.7MHz) 35.915 35.935 35.975 36.015 36.035 36.075 36.135 36.175 36.235 36.275
RX Counter Value (Ref. Freq. = 5.00kHz) 7183 7187 7195 7203 7207 7215 7227 7235 7247 7255
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April 10, 2000
Preliminary
HT9015
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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April 10, 2000

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